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CDC208 - Dual 1-Line To 4-Line Clock Drivers

General Description

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ąą D Low-Skew Propagation Delay Specifications for Clock-Driver Applications D TTL-Compatible Inputs and CMOS-Compatible Outputs D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise D EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (DW) CDC208 DUAL 1ĆLINE TO 4ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SCAS109F − APRIL 1990 − REVISED OCTOBER 1998 DW PACKAGE (TOP VIEW) 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 1 2 3 4 5 6 7 8 9 10 20 1Y1 19 1A 18 1OE1 17 1OE2 16 VCC 15 VCC 14 2A 13 2OE1 12 2OE2 11 2Y4 description The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum