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CDC208 - Dual 1-Line To 4-Line Clock Drivers

CDC208 Description

ąą D Low-Skew Propagation Delay Specifications for Clock-Driver Applications D TTL-Compatible Inputs and CMOS-Compatible Outputs D Flow-Through Archit.
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2).

CDC208 Applications

* D TTL-Compatible Inputs and CMOS-Compatible Outputs D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise D EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Optio

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Dual 1-Line 4-Line Clock Drivers Texas Instruments
Texas Instruments CDC208-like datasheet